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 MC74LVX132 Quad 2-Input NAND Schmitt Trigger
The MC74LVX132 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. Pin configuration and function are the same as the MC74LVX00, but the inputs have hysteresis. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features http://onsemi.com MARKING DIAGRAMS
14 14 1 SOIC-14 D SUFFIX CASE 751A 1 LVX132 AWLYWW
* * * * * * * *
High Speed: tPD = 5.8 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Low Noise: VOLP = 0.5 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available*
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 LVX 132 ALYW
14 SOEIAJ-14 M SUFFIX CASE 965 1 1 74LVX132 ALYW
14
A WL or L Y WW or W
= = = =
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
March, 2005 - Rev. 2
Publication Order Number: MC74LVX132/D
MC74LVX132
A1 1 3 B1 2 Y1 VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8
A2
4 6 Y2 1 A1 2 B1 3 Y1 4 A2 5 B2 6 Y2 7 GND
B2
5
Figure 2. Pin Connection (Top View)
A3 9 8 B3 10 Y3
FUNCTION TABLE
12 11 Y4 A Input L L H H B Input L H L H Y Output H H H L
A4
B4
13
Figure 1. Logic Diagram
ORDERING INFORMATION
Device MC74LVX132DR2 MC74LVX132DR2G MC74LVX132DT MC74LVX132DTR2 MC74LVX132M MC74LVX132MG MC74LVX132MEL MC74LVX132MELG Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) Shipping 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74LVX132
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 30% - 35% Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 85_C (Note 4) SOIC TSSOP SOIC TSSOP VI < GND VO < GND Parameter Value *0.5 to )7.0 *0.5 to )7.0 *0.5 to VCC )0.5 *20 $20 $25 $50 *65 to )150 260 )150 250 250 Level 1 UL 94-V0 @ 0.125 in > 2000 > 200 N/A $300 V Unit V V V mA mA mA mA _C _C _C _C/W mW
ILatchup
Latchup Performance
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO TA Dt/DV Supply Voltage Input Voltage Output Voltage Operating Free-Air Temperature Input Transition Rise or Fall Rate VCC = 3.0 V $0.3 V (Note 5) (HIGH or LOW State) Parameter Min 2.0 0 0 *40 0 Max 3.6 5.5 5.5 )125 100 Unit V V V _C ns/V
5. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
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MC74LVX132
II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIII I II II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I I IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
DC ELECTRICAL CHARACTERISTICS
Symbol VT+ Parameter Test Conditions VCC V 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 3.6 TA = 25C TA = 85C TA = 125C Min Max MinIIIMaxIII TypIIIMin Max 1.31 1.82 2.12 0.64 1.13 1.46 0.70 0.76 0.69 2.0 3.0 0.0 0.0 1.60 2.25 2.60 1.15 1.50 1.70 0.30 0.75 1.00 0.30 0.30 0.35 Unit V Positive Threshold Voltage (Figure 5) 1.15 1.50 1.70 0.30 0.75 1.00 0.30 0.30 0.35 1.60 2.25 2.60 0.90 1.45 1.90 1.30 1.50 1.60 1.15 1.50 1.70 0.30 0.75 1.00 0.30 0.30 0.35 1.60 2.25 2.60 0.90 1.45 1.90 1.30 1.50 1.60 VT- Negative Threshold Voltage (Figure 5) Hysteresis Voltage (Figure 5) 0.9 1.45 1.90 V VH 1.30 1.50 1.60 V VOH Minimum High-Level Output Voltage VIN = VIH or VIL IOH = - 50 mA IOH = - 50 mA IOH = - 4 mA 1.9 2.9 2.58 1.9 2.9 2.48 1.9 2.9 2.34 V VOL Maximum Low-Level Output Voltage VIN = VIH or VIL Maximum Input Leakage Current IOL = 50 mA IOL = 50 mA IOL = 4 mA 0.1 0.1 0.36 0.1 0.1 0.44 0.1 0.1 0.52 V Iin Vin = 5.5 V or GND 0.1 2.0 1.0 20 1.0 20 mA mA ICC Maximum Quiescent Supply Current Vin = VCC or GND
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter Test Conditions
TA = 25C Typ
TA = 85C
TA = 125C Min 1.0 1.0 1.0 1.0 Max
Min
Max
Min 1.0 1.0 1.0 1.0
Max
Unit ns
Maximum Propagation Delay, A or B to Y
VCC = 2.7V
CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF
7.0 10.0 5.8 8.3
11.0 16.0
13.0 18.7 12.5 17.5 1.5 1.5 10
15.0 20.0 14.5 19.5 1.5 1.5 10
VCC = 3.3 0.3V VCC = 2.7V
10.6 15.4 1.5 1.5 10
tOSHL, tOSLH Cin
Output to Output Skew (Note (N t 6) Maximum Input Capacitance
ns
VCC = 3.3 0.3V
CL = 50pF
4
pF
Typical @ 25C, VCC = 5.0 V 11
CPD
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.3 -0.3 Max 0.5 -0.5 2.0 0.8 Unit V V V V
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MC74LVX132
VCC A 50% GND tPLH Y 50% VCC tPHL
Figure 3. Switching Waveforms
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)
4
3
2
(VT+)
VHtyp (VT-)
1
2
2.5 3 3.5 VCC, POWER SUPPLY VOLTAGE (VOLTS) VHtyp = (VT+ typ) - (VT- typ)
4
Figure 5. Typical Input Threshold, VT+, VT- versus Power Supply Voltage
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MC74LVX132
VH Vin VCC VT+ VT- GND VOH Vout VOL (a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt-Trigger Offers Maximum Noise Immunity Vout VOL Vin VH VCC VT+ VT- GND VOH
Figure 6. Typical Schmitt-Trigger Applications
INPUT
Figure 7. Input Equivalent Circuit
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MC74LVX132
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
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EEE CCC EEE CCC
MC74LVX132
PACKAGE DIMENSIONS
SOEIAJ-14 M SUFFIX CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74LVX132/D


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